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1996 microchip technology inc. preliminary ds21176a-page 1 features single supply with operation down to 2.5v completely implements ddc1 ? /ddc2 ? interface for monitor identi?ation, including recovery to ddc1 improved noise immunity separate high speed 2-wire bus for microcontroller access to 4k-bit serial eeprom low power cmos technology 2 ma active current typical 20 m a standby current typical at 5.5v dual 2-wire serial interface bus, i 2 c ? compatible hardware write-protect for microcontroller access port self-timed write cycle (including auto-erase) page-write buffer for up to 8 bytes (ddc port) or 16 bytes (4k port) 100 khz (2.5v) and 400 khz (5v) compatibility 1,000,000 erase/write cycles guaranteed data retention > 40 years 8-pin pdip package available for extended temperature ranges description the microchip technology inc. 24LC41A is a dual-port 128 x 8 and 512 x 8-bit electrically erasable prom (eeprom). this device is designed for use in applica- tions requiring storage and serial transmission of con- ?uration and control information. three modes of operation have been implemented: transmit-only mode for the ddc monitor port bi-directional mode for the ddc monitor port bi-directional, industry-standard 2-wire bus for the 4k microcontroller access port upon power-up, the ddc monitor port will be in the transmit-only mode, repeatedly sending a serial bit stream of the entire memory array contents, clocked by the vclk pin. a valid high to low transition on the dscl pin will cause the device to enter the transition mode, an look for a valid control byte on the i 2 c bus. if it detects a valid control byte from the master, it will switch to bi-directional mode, with byte selectable read/write capability of the memory array using dscl. if no con- trol byte is received, the device will revert to the trans- mit-only mode after it received 128 consecutive vclk - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c package type block diagram pulses while the dscl pin is idle. the 4k-bit microcon- troller port is completely independent of the ddc port, therefore, it can be accessed continuously by a micro- controller without interrupting ddc transmission activ- ity. the 24LC41A is available in a standard 8-pin pdip package in both commercial and industrial temperature ranges. 24LC41A pdip dscl vclk v ss msda 1 2 3 4 dsda vcc mwp mscl 8 7 6 5 edid table 1k-bit 4k-bit serial eeprom msda mscl ddc monitor port microcontroller access port dsda vclk dscl 24LC41A 1k/4k 2.5v dual mode, dual port i 2 c ? serial eeprom ddc is a trademark of video electronics standards association. i 2 c is a trademark of philips corporation. this document was created with framemake r404
24LC41A ds21176a-page 2 preliminary 1996 microchip technology inc. 1.0 electrical characteristics 1.1 maxim um ratings* v cc ........................................................................7.0v all inputs and outputs w.r.t. v ss .... -0.6v to v cc +1.0v storage temperature .......................... -65?c to +150?c ambient temp. with power applied ..... -65?c to +125?c soldering temperature of leads (10 seconds) .. +300?c esd protection on all pins ..................................... 3 4 kv * notice: stresses above those listed under ?aximum ratings?may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function dscl serial clock for ddc bi-directional mode (ddc2) dsda serial address and data i/o (ddc bus) vclk serial clock for ddc transmit-only mode (ddc1) mscl serial clock for 4k-bit mcu port msda serial address and data i/o for 4k-bit mcu port mwp hardware write-protect for microcon- troller access port v ss ground v cc +2.5v to +5.5v power supply table 1-2: dc characteristics v cc = +2.5v to 5.5v commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter symbol min max units conditions dscl, dsda, mscl & msda pins: high level input voltage low level input voltage v ih v il .7 v cc .3 v cc v v input levels on vclk pin: high level input voltage low level input voltage v ih v il 2.0 .8 .2 v cc v v v cc 3 2.7v (note) v cc < 2.7v (note) hysteresis of schmitt trigger inputs v hys .05 v cc v note 1 low level output voltage v ol 1 ?4vi ol = 3 ma, v cc = 2.5v (note) low level output voltage v ol 2 ?6vi ol = 6 ma, v cc = 2.5v input leakage current i li -10 10 m av in =.1v to v cc output leakage current i lo -10 10 m av out =.1v to v cc pin capacitance (all inputs/outputs) c in , c out ?0pfv cc = 5.0v (note), tamb = 25 c, f clk = 1 mhz operating current i cc write i cc read 3 1 ma ma v cc = 5.5v, dscl or mscl = 400 khz standby current i ccs 60 200 m a m a v cc = 3.0v, dsda or msda = dscl or mscl = v cc v cc = 5.5v, dsda or msda = dscl or mscl = v cc note: this parameter is periodically sampled and not 100% tested.
1996 microchip technology inc. preliminary ds21176a-page 3 24LC41A table 1-3: ac characteristics (ddc monitor and microcontroller access ports) ddc monitor port (bi-directional mode) and microcontroller access port parameter symbol standard mode vcc = 4.5 - 5.5v fast mode units remarks min max min max clock frequency (dscl and mscl) f clk 100 400 khz clock high time (dscl and mscl) t high 4000 600 ns clock low time (dscl and mscl) t low 4700 1300 ns dscl, dsda, mscl & msda rise time t r 1000 300 ns (note 1) dscl, dsda, mscl & msda fall time t f 300 300 ns (note 1) start condition hold time t hd : sta 4000 600 ns after this period the ?st clock pulse is generated start condition setup time t su : sta 4700 600 ns only relevant for repeated start condition data input hold time t hd : dat 0 0 ns (note 2) data input setup time t su : dat 250 100 ns stop condition setup time t su : sto 4000 600 ns output valid from clock t aa 3500 900 ns (note 2) bus free time t buf 4700 1300 ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of 250 20 + .1 c b 250 ns (note 1), c b 100 pf input ?ter spike suppres- sion (dscl, dsda, mscl & msda pins) t sp 50 50 ns (note 3) write cycle time t wr 10 10 ms byte or page mode endurance 10m 10m cycles 25 c, vcc = 5.0v, block mode (note 4) ddc monitor port transmit-only mode parameters output valid from vclk t vaa 2000 1000 ns vclk high time t vhigh 4000 600 ns vclk low time t vlow 4700 1300 ns vclk setup time t vhst 0 0 ns vclk hold time t spvl 4000 600 ns mode transition time t vhz 500 500 ns transmit-only power up time t vpu 0 0 ns input ?ter spike suppression (vclk pin) t spv 100 100 ns note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the unde?ed region (minimum 300 ns) of the falling edge of dscl or mscl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys speci?ations are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a t i speci?ation for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? appli- cation, please consult the total endurance model which can be obtained on our bbs or website.
24LC41A ds21176a-page 4 preliminary 1996 microchip technology inc. 2.0 functional description 2.1 ddc monitor p or t the ddc monitor port operates in two modes, the transmit-only mode and the bi-directional mode. there is a separate 2-wire protocol to support each mode, each having a separate clock input and sharing a com- mon data line (dsda). the device enters the transmit- only mode upon power-up. in this mode, the device transmits data bits on the dsda pin in response to a clock signal on the vclk pin. the device will remain in this mode until a valid high to low transition is placed on the dscl input. when a valid transition on dscl is rec- ognized, the device will switch into the bi-directional mode and look for its control byte to be sent by the mas- ter. if it detects its control byte, it will stay in the bi-direc- tional mode. otherwise, it will revert to the transmit- only mode after it sees 128 vclk pulses. 2.1.1 transmit-only mode the device will power up in the transmit-only mode at address 00h. this mode supports a unidirectional 2- wire protocol for transmission of the contents of the memory array. this device requires that it be initialized prior to valid data being sent in the transmit-only mode (see section 2.1.2). in this mode, data is transmitted on the dsda pin in 8-bit bytes, each followed by a ninth, null bit (see figure 2-1). the clock source for the trans- mit-only mode is provided on the vclk pin, and a data bit is output on the rising edge on this pin. the eight bits in each byte are transmitted by most signi?ant bit ?st. each byte within the memory array will be output in sequence. when the last byte in the memory array is transmitted, the output will wrap around to the ?st loca- tion and continue. the bi-directional mode clock (dscl) pin must be held high for the device to remain in the transmit-only mode. 2.1.2 initialization procedure after v cc has stabilized, the device will be in the trans- mit-only mode. nine clock cycles on the vclk pin must be given to the device for it to perform internal sychroni- zation. during this period, the dsda pin will be in a high impedance state. on the rising edge of the tenth clock cycle, the device will output the ?st valid data bit which will be the most signi?ant bit of a byte. the device will power up at an indeterminate byte address (see figure 2-2). figure 2-1: transmit-only mode figure 2-2: device initialization scl sda vclk t vaa t vaa bit 1 (lsb) null bit bit 1 (msb) bit 7 t vlow t vhigh t vaa t vaa bit 8 bit 7 high impedance for 9 clock cycles t vpu 12 891011 scl sda vclk v cc
1996 microchip technology inc. preliminary ds21176a-page 5 24LC41A 2.1.3 bi-directional mode before the 24LC41A can be switched into the bi-direc- tional mode (figure 2-4), it must enter the transition mode, which is done by applying a valid high to low transition on the bi-directional mode clock (dscl). as soon it enters the transition mode, it looks for a control byte 1010 000x on the i 2 c ? bus, and starts to count pulses on vclk. any high to low transition on the dscl line will reset the count. if it sees a pulse count of 128 on vclk while the dscl line is idle, it will revert back to the transmit-only mode, and transmit its contents starting with the most signi?ant bit in address 00h. however, if it detects the control byte on the i 2 c bus, (figure 2-3) it will switch to the in the bi-directional mode. once the device has made the transition to the bi-directional mode, the only way to switch the device back to the transmit-only mode is to remove power from the device. the mode transition process is shown in detail in figure 2-4. once the device has switched into the bi-directional mode, the vclk input is disregarded, with the excep- tion that a logic high level is required to enable write capability. this mode supports a two-wire bi-directional data transmission protocol (i 2 c ) . in this protocol, a device that sends data on the bus is de?ed to be the transmitter, and a device that receives data from the bus is de?ed to be the receiver. the bus must be con- trolled by a master device that generates the bi-direc- tional mode clock (dscl), controls access to the bus and generates the start and stop conditions, while the monitor port acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. in the bi-directional mode, the monitor port only responds to commands for device 1010 000x. 2.2 micr ocontr oller access p or t the microcontroller access port supports a bi-direc- tional 2-wire bus and data transmission protocol. a device that sends data onto the bus is de?ed as trans- mitter, and a device receiving data as receiver. the bus has to be controlled by a master device which gener- ates the serial clock (mscl), controls the bus access, and generates the start and stop conditions, while the microcontroller access port works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is acti- vated. figure 2-3: successful mode transition to bi-directional mode figure 2-4: mode transition with recovery to transmit-only mode transition mode with possibility to return to transmit-only mode bi-directional permanently scl sda vclk count = 1 2 n 0 vclk transmit only mode mode s1010 0 0 0 0 ack n < 128 tvhz scl sda vclk transmit only mode bi-directional recovery to transmit-only mode bit8 (msb of data in 00h) vclk count = 1 2 3 4 127 128
24LC41A ds21176a-page 6 preliminary 1996 microchip technology inc. figure 2-5: display operation per ddc standard proposed by vesa communication is idle is vsync present? no send edid continuously using vsync as clock high to low transition on scl? no yes yes stop sending edid. switch to ddc2 mode. display has transition state ? optional set vsync counter = 0 change on vclk lines? scl, sda or no yes high - low transition on scl ? reset vsync counter = 0 no yes valid received? ddc2 address no no vclk cycle? yes increment vclk counter yes switch back to ddc1 mode. ddc2 communication idle. display waiting for address byte. ddc2b address received? yes receive ddc2b command respond to ddc2b command is display access.bus tm yes valid access.bus address? no yes see access.bus speci?ation to determine correct procedure. yes no yes no no no display power-on or ddc circuit powered from +5 volts or start timer reset counter or timer (if appropriate) counter=128 or timer expired? high to low transition on scl? no yes note 1: the base ?wchart is copyright 1993, 1994, 1995 video electronic standard association (vesa) from vesas display data channel (ddc) standard proposal ver. 2p rev. 0, used by permission of vesa. 2: the dash box and text ?he 24LC41A and ... inside dash box.?are added by microchip technology, inc. 3: vsync signal is normally used to derive a signal for vclk pin on the 24LC41A. capable? the 24LC41A was designed to comply to the portion of ?wchart inside dash box.
1996 microchip technology inc. preliminary ds21176a-page 7 24LC41A 3.0 bi-directional bus characteristics characteristics for the bi-directional bus are identical for both the ddc monitor port (in bi-directional mode) and the microcontroller access port the following bus protocol has been de?ed: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been de?ed (see figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 star t data t ransf er (b) a high to low transition of the dsda or msda line while the clock (dscl or mscl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data t ransf er (c) a low to high transition of the dsda or msda line while the clock (dscl or mscl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data v alid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur, it will replace data in a ?st in ?st out fashion. 3.5 ac kno wledg e each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit . the device that acknowledges has to pull down the dsda or msda line during the acknowledge clock pulse in such a way that the dsda or msda line is sta- ble low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowl- edge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop con- dition. 3.6 de vice ad dressing a control byte is the ?st byte received following the start condition from the master device. the ?st part of the control byte consists of a 4-bit control code. this control code is set as 1010 for both read and write oper- ations and is the same for both the ddc monitor port and microcontroller access port. the next three bits of the control byte are block select bits (b1, b2, and b0). all three of these bits are zero for the ddc monitor port. the b2 and b1 bits are don? care bits for the microcon- troller access port, and the b0 bit is used by the micro- controller access port to select which of the two 256 word blocks of memory are to be accessed (see figure 3-4). the b0 bit is effectively the most signi?ant bit of the word address. the last bit of the control byte de?es the operation to be performed. when set to one, a read operation is selected; when set to zero, a write operation is selected. following the start condition, the device monitors the dsda or msda bus checking the device type identi?r being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the device will select a read or a write operation. the ddc monitor port and microcontroller access port can be accessed simultaneously because they are com- pletely independent of one another. note: the microcontroller access port and the ddc monitor port (in bi-directional mode) will not generate any acknowledge bits if an internal programming cycle is in progress. operation control code chip select r/w read 1010 b1b2b0 1 write 1010 b1b2b0 0
24LC41A ds21176a-page 8 preliminary 1996 microchip technology inc. figure 3-1: data transfer sequence on the serial bus figure 3-2: bus timing start/stop figure 3-3: bus timing data figure 3-4: control byte allocation dscl dsda ( a ) (b) (d) (d) (c) ( a ) start condition address or acknowledge valid data allowed to change stop condition or mscl or msda mscl dsda t su : sta t hd : sta start stop v hys t su : sto or mscl in or msda in dscl dsda dsda t hd : sta t su : sta t f t high t r t su : sto t su : dat t hd : dat t buf t aa t hd : sta t aa t sp t low or mscl in or msda in or msda out b0, b1, and b2 are zeros for ddc monitor port. b1 and b2 are don? care bits for the microcontroller access port, and b0 is used to select which of the two 256 word blocks of memory are to be accessed. r/w a 1 010b1b2b0 read/write start slave address
1996 microchip technology inc. preliminary ds21176a-page 9 24LC41A 4.0 write operation write operations are identical for the ddc monitor port (when in bi-directional mode) and the microcontroller access port, with the exception of the vclk and mwp pins noted in the next sections. data can be written using either a byte write or page write command. write commands for the ddc monitor port and the microcon- troller access port are completely independent of one another. 4.1 b yte write following the start signal from the master, the slave address (4-bits), the chip select bits (3-bits) and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the port. after receiving another acknowledge signal from the port, the master device will transmit the data word to be written into the addressed memory location. the port acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time, the port will not generate acknowledge signals (see figure 4-1). for the ddc monitor port it is required that vclk be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that vclk can go low while the device is in its self- timed program operation and not affect programming. the mwp pin must be held high for the duration of the write protection. 4.2 p a g e write the write control byte, word address, and the ?st data byte are transmitted to the port in the same way as in a byte write. but, instead of generating a stop condition, the master transmits up to eight data bytes to the ddc monitor port or 16 bytes to the microcontroller access port, which are temporarily stored in the on-chip page buffer and will be written into the memory after the mas- ter has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order 5- bits of the word address remains constant. if the master should transmit more than eight words to the ddc mon- itor port or 16 words to the microcontroller access port prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (see figure 4-2). for the ddc monitor port, it is required thatvclk be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that vclk can go low while the device is in its self- timed program operation and not affect programming. for the ddc monitor port, the mwp pin must be held high for the duration of the write cycle. figure 4-1: byte write s p s t a r t s t o p bus activity master sda or bus activity a c k a c k a c k control byte word address data msda line vclk
24LC41A ds21176a-page 10 preliminary 1996 microchip technology inc. figure 4-2: page write figure 4-3: vclk write enable timing s p bus activity master dsda or bus activity s t a r t s t o p control byte word address (n) data n datan + 7 datan + 1 a c k a c k a c k a c k a c k msda line vclk scl sda in vclk t vhst t spvl t hd : sta t su : sto 5.0 acknowledge polling acknowledge polling can be done for both the ddc monitor port (when in bi-directional mode) and the microcontroller access port. since the port will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize but throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w =0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the ?w diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
1996 microchip technology inc. preliminary ds21176a-page 11 24LC41A 6.0 write protection 6.1 ddc monitor p or t when using the ddc monitor port in the bi-directional mode, the vclk pin operates as the write protect con- trol pin. setting vclk high allows normal write opera- tions, while setting vclk low prevents writing to any location in the array. connecting the vclk pin to v ss would allow the monitor port to operate as a serial rom, although this con?uration would prevent using the device in the transmit-only mode. 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. these operations are identical for both the ddc monitor port (in bi-directional mode) and the microcontroller access port and are completely independent of one another. 7.1 current ad dress read the port contains an address counter that maintains the address of the last word accessed, internally incre- mented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the port issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop con- dition and the port discontinues transmission (see figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, ?st the word address must be set. this is done by sending the word address to the port as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a one. the port then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does gen- erate a stop condition and the port discontinues trans- mission (see figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the port transmits the ?st data byte, and the master issues an acknowledge as opposed to a stop condition in a random read. this directs the port to transmit the next sequentially addressed 8-bit word (see figure 7-3). to provide sequential reads, the port contains an inter- nal address pointer, which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation.
24LC41A ds21176a-page 12 preliminary 1996 microchip technology inc. 7.4 noise pr otection both the ddc monitor port and microcontroller access port employ a v cc threshold detector circuit which dis- ables the internal erase/write logic, if the v cc is below 1.5 volts at nominal conditions. the vclk, dscl, mscl, dsda, and msda inputs have schmitt trigger and ?ter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 7-1: current address read figure 7-2: random read figure 7-3: sequential read sp bus activity master dsda or bus activity s t a r t control byte data n a c k n o a c k s t o p msda line s p s bus activity master msda line bus activity s t a r t s t o p control byte word address (n) data n a c k a c k n o a c k control byte a c k s t a r t p dsda or bus activity s t o p control byte data n a c k n o a c k a c k a c k a c k data n + 1 data n + 2 data n + x bus activity master msda line
1996 microchip technology inc. preliminary ds21176a-page 13 24LC41A 8.0 pin descriptions 8.1 dsd a this pin is used to transfer addresses and data into and out of the ddc monitor port, when the device is in the bi-directional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the dsda pin. this pin is an open drain terminal, therefore the dsda bus requires a pullup resistor to v cc (typical 10k w for 100 khz, 1k w for 400 khz). for normal data transfer in the bi-directional mode, dsda is allowed to change only during dscl or msda low. changes during dscl high are reserved for indi- cating the start and stop conditions. 8.2 dscl this pin is the clock input for the ddc monitor port while in the bi-directional mode, and is used to synchro- nize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit-only mode to the bi-directional mode. it must remain high for the chip to continue operation in the transmit-only mode. 8.3 vclk this pin is the clock input for the ddc monitor port while in the transmit-only mode. in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in the bi-directional mode, a high logic level is required on this pin to enable write capability. 8.4 mwp this pin is used to write protect the 4k memory array for the microcontroller access port. this pin must be connected to either v ss or v cc . if tied to vss, normal memory operation is enabled (read/write the entire memory). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. 8.5 m scl this pin is the clock input for the microcontroller access port, and is used to synchronize data transfer to and from the device. 8.6 msd a this pin is used to transfer addresses and data into and out of the microcontroller access port. this pin is an open drain terminal, therefore the msda bus requires a pullup resistor to v cc (typical 10k w for 100 khz, 1k w for 400 khz). msda is allowed to change only during mscl low. changes during mscl high are reserved for indicating the start and stop conditions.
24LC41A ds21176a-page 14 preliminary 1996 microchip technology inc. notes:
24LC41A 1996 microchip technology inc. preliminary ds21176a-page 15 24LC41A pr oduct identi cation system to order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales of?es. package: p = plastic dip (300 mil), 8-lead temperature blank = 0 c to +70 c range: i = -40 c to +85 c device: 24LC41A dual mode, dual port cmos serial eeprom 24LC41A /p
ds21176a-page 16 preliminary 1996 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no repre- sentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not autho- rized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. w orldwide s ales & s ervice asia/pacific china microchip technology unit 406 of shanghai golden bridge bldg. 2077 yan?n road west, hongiao district shanghai, peoples republic of china tel: 86 21 6275 5700 fax: 011 86 21 6275 5060 hong kong microchip technology rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 india microchip technology no. 6, legacy, convent road bangalore 560 025 india tel: 91 80 526 3148 fax: 91 80 559 9840 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan, r.o.c microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 1628 850303 fax: 44 1628 850178 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleone pas taurus 1 viale colleoni 1 20041 agrate brianza milan italy tel: 39 39 6899939 fax: 39 39 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/3/96 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972 991-7177 fax: 972 991-8588 dayton microchip technology inc. suite 150 two prestige place miamisburg, oh 45342 tel: 513 291-1654 fax: 513 291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714 263-1888 fax: 714 263-1338 new york microchip technmgy inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905 405-6279 fax: 905 405-6253 all rights reserved. 1996, microchip technology incorporated, usa. 9/96 printed on recycled paper.

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